TELKOMNIKA Telecommunication Computing Electronics and Control Vol.
No.
April 2026, pp.
ISSN: 1693-6930.
DOI: 10.
12928/TELKOMNIKA.
A counter-centric binary-to-binary coded decimal and multiplexed seven-segment driver on an Artix-7 FPGA Ahmed Mohamed Abdellatif Abdelrahman Elngar.
Muhamad S.
Mauladdawilah.
Tariq H.
Alomary Department of Electrical and Computer Engineering.
Faculty of Engineering.
King Abdulaziz University.
Jeddah.
Saudi Arabia
Article Info
ABSTRACT
Article history:
This paper presents a complete field-programmable gate array (FPGA) implementation for showing a 4-bit binary value .
Ae.
as a two-digit decimal number on the Nexys-4 double data rate (DDR) seven-segment display.
The design comprises: .
a compact binary-to-binary-coded decimal (BCD) converter tailored to the 0Ae15 range.
a seven-segment decoder for activelow, common-anode digits.
a counter-based clock-enable controller that time-multiplexes the digits at a rate chosen to be flicker-free yet energyefficient.
A simple timing model links the divider width ycA, the number of digits ycAya , and the refresh rate yceframe = yceclk /.
cAya 2ycA ).
Simulation verified hazard-free switching and one-hot anode selection.
hardware tests on the Nexys-4 DDR .
MHz cloc.
confirmed the analysis.
Selecting ycA = 18 yields ycdwell = 2.
62144 ms and yceframe OO 190.
7 Hz, which removes ghosting while avoiding unnecessary high-frequency scanning.
The system displays all inputs correctly and provides a clear sizing rule for wider inputs and more The approach is fully synthesizable, resource-light, and portable to larger word-lengths and displays.
Received Oct 16, 2025 Revised Jan 7, 2025 Accepted Jan 30, 2026 Keywords:
Artix-7
Binary to binary coded decimal Field programmable gate array
Multiplexing Seven-segment display
VHDL
This is an open access article under the CC BY-SA license.
Corresponding Author:
Ahmed M.
Elngar Department of Electrical and Computer Engineering.
Faculty of Engineering King Abdulaziz University Jeddah.
Saudi Arabia Email: Ahmedelngar02@gmail.
INTRODUCTION
Seven-segment displays remain a widely used and practical method for presenting numerical information in digital systems, owing to their low cost, simplicity, and clear visual output .
, .
Although such displays operate in decimal form, digital hardware represents values in binary.
Bridging this difference requires conversion logic that reliably maps binary inputs to human-readable digits.
Field programmable gate array (FPGA) development boards, including the Nexys-4 double data rate (DDR) used in this work, provide multi-digit seven-segment displays in which all digits share the same segment lines .
, .
Because of this shared-bus structure, only one digit can be driven at a time, and the system must scan the digits one after another.
When the scanning is fast enough, above the human flicker threshold, the display appears steady .
, .
This paper presents the complete design and implementation of a system that converts a 4-bit binary input .
Ae.
into two decimal digits and displays them on the Nexys-4 DDR seven-segment interface.
Two technical challenges are addressed.
The first is the accurate conversion of the binary input into its tens and units digits, which requires compact and efficient logic suitable for FPGA implementation .
, .
The second is the design of a scanning mechanism that activates each digit in turn at a rate that avoids visible flicker while Journal homepage: http://journal.
id/index.
php/TELKOMNIKA TELKOMNIKA Telecommun Comput El Control minimising power consumption.
If the refresh rate is too fast, unnecessary switching increases dynamic power.
if too slow, flicker or ghosting becomes visible .
, .
To meet these goals, the system uses a clock-enable pulse derived from the 100 MHz system clock, allowing precise control over the scanning rate without gating or dividing the main clock.
This approach follows recommended FPGA timing practices, avoiding skew and timing uncertainty while keeping the logic synchronous .
, .
The use of a tunable enable pulse also makes it possible to study refresh-rate behaviour analytically and experimentally, enabling the optimal balance between power reduction and visual smoothness .
, .
The key contributions of this work are summarised as follows:
Oe Counter-centric multiplexing architecture: a novel approach to display multiplexing that operates at the minimum refresh rate necessary to eliminate visual flicker (OO100-120 H.
, .
, significantly reducing power consumption compared to conventional high-frequency scanning methods .
while maintaining display quality and brightness uniformity.
Oe Optimised binary-to- binary-coded decimal (BCD) conversion: an efficient conversion algorithm specifically tailored for the 0-15 input range, utilising Boolean minimisation techniques and K-map optimisation .
to achieve minimal logic resource utilisation while ensuring accurate tens and units digit separation .
The rest of the paper is organised as: section 2 reviews related work on seven-segment driving, binaryto-decimal conversion, and display scanning.
Section 3 explains the architecture and design choices.
Section 4 reports simulation and hardware results.
Section 5 concludes and outlines extensions.
RELATED WORK
Research on efficient seven-segment display control and binary-to-BCD conversion connects foundational logic design with perceptual requirements and power optimisation for FPGA platforms.
The literature is divided into several relevant domains:
Classic logic minimisation techniques have long been central to segment-level decoder design.
Canonical methods such as Karnaugh maps .
QuineAeMcCluskey algebraic reduction .
, and heuristic approaches like the Espresso algorithm .
allow for the creation of compact, hazard-free Boolean These techniques remain valuable for developing segment decoders implemented on FPGA lookup table (LUT) fabrics, promoting resource efficiency, especially in instructional and low-complexity applications .
For binary-to-BCD conversion, small-scale ranges like 0Ae15 typically rely on direct truth-table encoding or simple combinational adder networks, which are practical for simple displays .
However, for broader ranges or scalable systems, the shift-and-add-3 Audouble-dabbleAy algorithm is preferable for its iterative, linear scaling properties .
Area and latency trade-offs between combinational, iterative, and hybrid conversion circuits inform the selection of architectures for FPGA teaching boards, where reuse and modularity are valued .
In the context of multi-digit display driving, the shared-segment architecture of modern teaching FPGAs necessitates time-division multiplexing, as only one digit can be illuminated at a time .
Psychophysical studies set the typical flicker-fusion threshold at approximately 60 Hz .
thus, engineering rebuttals aim for refresh rates above 100 Hz per digit to ensure the display appears uniformly bright and stable across all viewing conditions .
Notably, since dynamic power consumption in CMOS circuits is directly proportional to switching activity .
cE Oy yceyaycO 2 ) .
, .
, academic and industrial guidelines advocate the use of clock-enable signals, derived from the master system clock, to control multiplexing rate, thus minimising unnecessary transitions and maintaining optimal FPGA timing integrity .
, .
Finally, practical implementations must adhere to hardware standards and board documentation, such as the Ie Std 1164 logic types .
and official platform reference manuals .
These dictate segment polarity, input/output (I/O) standards, and pin mappings, directly shaping truth-table derivations and the functional correctness of display controllers .
Collectively, these works establish the foundational principles and constraints that motivate this paperAos proposed architecture: a combination of a compact binary-to-BCD converter, optimally minimised decoder logic, and a power-conscious, clock-enable-based multiplexing strategy.
DESIGN AND IMPLEMENTATION
This section describes the end-to-end design that converts a 4-bit binary input into two decimal digits and displays them on the Nexys-4 DDR seven-segment interface.
The overall structure is shown in Figure 1.
The datapath consists of three functional blocks: .
a binary-to-BCD stage that produces AutensAy and AuunitsAy.
a seven-segment encoder that converts each decimal digit into segment patterns.
a scanning A counter-centric binary-to- binary coded decimal and multiplexed A (Ahmed M.
Elnga.
A ISSN: 1693-6930 controller that selects one display digit at a time.
All logic is synchronous to the 100 MHz system clock, and the scan is advanced by a short enable pulse.
the main clock is never gated.
Figure 1.
System architecture block diagram System model and signals The input is a 4-bit number ycu OO .
captured from slide switches.
The binary-to-BCD stage outputs two 4-bit nibbles BCDtens and BCDunits .
A small selector chooses which nibble feeds the seven-segment encoder.
The encoder drives the shared segment bus seg.
: .
Ae.
Because the Nexys-4 DDR uses common-anode displays, the segments are active-low .
ogic Ao0Ao turns a light-emitting diode (LED) o.
and each digit is enabled by an active-low anode line.
Only one anode is asserted at a time, so only one digit is lit at any instant.
The scan controller rotates the active anode and presents the matching segment pattern in step with it.
The complete data and control paths are summarised in Figure 1.
The BIN2BCD module yields five BCD nibbles from a 16-bit input.
a 5:1 multiplexer forwards the selected nibble to the S7D decoder while the multiplex controller advances the active-low anode enable and maintains a fixed dwell per digit with a counterderived clock-enable.
Binary-to-BCD conversion For the 4-bit case the conversion is simple and exact.
The AutensAy digit is either Ao0Ao or Ao1Ao:
ycc10 = { 0, ycu O 9, ycc = ycu Oe 10 UI ycc10 1, ycu Ou 10, 1 This avoids a general divider and keeps logic usage low.
The output nibbles BCDtens and BCDunits are then passed to the encoder.
The encoder implements the standard 0Ae9 segment patterns in active-low form.
Table 1 lists the truth table for digits 0Ae9 .
ows aAeg, where Ao0Ao means AuLED onA.
This table is the basis for the Boolean minimisation used in the register-transfer level (RTL).
Table 1.
Units digit: active-low segment truth table .
= ON, 1 = OFF) BCD Seven-segment encoding Each BCD nibble is mapped to seg.
: .
by compact Boolean expressions obtained from the truth The encoder outputs are registered, so the segment bus changes only on a clock edge.
Registering the outputs ensures that segment values remain constant while a digit is enabled, which removes visible AughostingAy when the scan advances to the next digit.
TELKOMNIKA Telecommun Comput El Control.
Vol.
No.
April 2026: 676-684 TELKOMNIKA Telecommun Comput El Control Scan controller and timing model The scan is advanced by a clock-enable pulse produced by a binary counter of width ycA.
If ycNclk is the 100 MHz clock period, then the enable pulse repeats every.
ycdwell = 2ycA ycNclk with ycAya display digits, one full frame takes, ycframe = ycAya ycdwell , yceframe = ycframe ycAya 2 ycA where ycAya is the number of scanned digits.
The dominant switching arises from .
segment updates when the currently displayed digit changes, and .
the active-low, one-hot anode lines.
Let yaframe denote the total Hamming distance between consecutive seven-segment patterns over one full frame .
ontent-dependen.
relative dynamic power index is defined as:
PI = ycseg yceframe yaframe ycan .
ycAya ) yceframe .
with non-negative weights ycseg , ycan used to aggregate the two contributions.
The index is unitless and intended for comparative assessment across .
cA, ycAya ) and typical digit contents.
Choosing ycA to keep yceframe in the O 100Ae 200 Hz band reduces switching while maintaining a steady display.
Parameterisation and scalability The design is parameterised by the number of input bits ycAyaA and the number of digits ycAya .
In general, ycAya = UOlog10 .
ycAyaA )UO = UOycAyaA UI log10 2UO For wider inputs .
, 8, 12, or 16 bit.
, a small iterative binary-to-BCD core can be used, while the selector, encoder and scanning logic remain unchanged.
The same timing model applies: choose ycA to place yceframe in the 100Ae200 Hz band for flicker-free presentation with low switching activity.
A brief sizing table for ycA versus ycAya is provided with the results.
Implementation details Pin assignments map the three switches to the input bits and the shared segment lines to seg.
: .
The anode vector is wired to the first two digits of the eight-digit module on the Nexys-4 DDR.
All outputs that drive the display .
egments and anode.
are registered.
The constraints file sets the 100 MHz clock and I/O standards.
Verification plan Unit tests: exhaustively stimulate the binary-to-BCD converter .
Ae.
and the BCD Ie seven-segment encoders .
Ae.
, checking against Table 1 .
ctive-lo.
Integration sim: run the multiplex FSM with a shortened divider and confirm enable-synchronised updates and opposite anode drive.
On-board: program the device, sweep inputs, and capture photos.
Tune ycA if needed to remove ghosting while keeping ycedigit Ou 100 Hz.
RESULTS AND DISCUSSION
A staged verification flow was used: unit-level simulation of the clock-divider, multiplexer and sevensegment decoder.
integrated simulation of the whole display path.
and finally on-board tests on the Nexys-4 DDR.
The consolidated timing diagram in Figure 2 shows the key internal signals .
small divider value was used in simulation purely for visibilit.
Clock-enable pulses occur every 2ycA ycNclk .
on each pulse the digit index sel_idx increments by one, the active-low anodes present a one-hot selection for the addressed digit, and the registered segment bus remains constant throughout each dwell.
Two points are evident: .
there are no hazards or intermediate glitches at selection boundaries, confirming that the segment data only update synchronously on the clock-enable edge.
non-selected anodes remain de-asserted for the full dwell, removing the conditions that typically produce AughostingAy.
With yceclk = 100 MHz and the implementation setting ycA = 18, the measured dwell and frame timings match the analytical model:
ycdwell = 2ycA ycNclk = 2.
62144 ms, ycframe = ycAya ycdwell = 5.
24288 ms .
cAya = .
A counter-centric binary-to- binary coded decimal and multiplexed A (Ahmed M.
Elnga.
A ISSN: 1693-6930 During early trials a faint after-image on the inactive digit indicated an overly high multiplex rate, the next digit was enabled before the previous drivers had fully released.
Guided by the timing model ycdwell = 2ycA ycNclk , ycframe = ycAya ycdwell , yceframe = 1/ycframe , we swept the divider width ycA around the perceptual limit.
A low-power target of OO 100 Hz suggests ycA OO log2 .
ms/10 n.
OO 18.
, ycA = .
Empirically, values near 19 still showed trace ghosting on our board revision.
ycA = 18 gave ycdwell = 2.
62144 ms, ycframe = 5.
24288 ms and yceframe OO 190.
7 Hz .
bout 95 Hz effective per digi.
, which removed the artefact while remaining comfortably flicker-free.
Figure 2.
Timing diagram of the clock-enable driven multiplexing To quantify the refreshAepower trade-off.
Figure 3 plots a relative dynamic-power index against the divider ycA for ycAya OO .
,3,4,.
at yceycaycoyco = 100 MHz.
The index is proportional to the number of segments and anode transitions per second.
hence, lower values imply lower switching power.
Two trends are evident.
First, power falls nearly exponentially with ycA: every increment of ycA halves the frame rate yceyceycycaycoyce = yceycaycoyco /.
cAya 2ycA ) and correspondingly reduces switching activity.
Second, for a fixed ycA, power rises with the number of digits ycAya because more anodes are scanned each frame.
The marker highlights .
cAya = 2, ycA = .
, which sits in the elbow of the curve, well above the flicker-fusion threshold (OO 190.
7 Hz frame rat.
yet noticeably lower power than faster scans at ycA = 16 or ycA = 17.
Moving to ycA = 19 would reduce power further, but pushes the refresh close to O 100 Hz, narrowing timing margin and, on our board revision, re-introducing slight ghosting.
These observations align with the analytical sizing in Table 2.
Figure 3.
Relative dynamic power versus divider ycA for ycAya OO .
,3,4,.
at yceycaycoyco = 100 MHz Table 2.
Refresh and relative switching activity versus digit count on a 100 MHz clock Case ycAyc .
Ae.
Ae.
Ae4.
Ae65.
ycAyc .
Target yeNframe OO 190 Hz OO 200 Hz OO 150 Hz OO 120 Hz Choose ycA Result yeNframe 73 Hz 31 Hz 73 Hz 59 Hz yeidwell 621 ms 311 ms 311 ms 311 ms Power index .
TELKOMNIKA Telecommun Comput El Control.
Vol.
No.
April 2026: 676-684 TELKOMNIKA Telecommun Comput El Control Taken together, these results confirm that the architecture meets its aims: the MUX and controller behave correctly in simulation.
the hardware achieves flicker-free, ghost-free output at a modest refresh rate that lowers dynamic power.
and end-to-end correctness is maintained for every input in the 4-bit range, as evidenced by Figures 4.
Ae.
Figure 4.
Hardware test results.
Input 0000 displays Au00Ay, .
Input 0001 displays Au01Ay, .
Input 0010 displays Au02Ay, .
Input 0011 displays Au03Ay, .
Input 0100 displays Au04Ay, .
Input 0101 displays Au05Ay, .
Input 0110 displays Au06Ay, .
Input 0111 displays Au07Ay, .
Input 1000 displays Au08Ay, .
Input 1001 displays Au09Ay, .
Input 1010 displays Au10Ay, .
Input 1011 displays Au11Ay, .
Input 1100 displays Au12Ay, .
Input 1101 displays Au13Ay, .
Input 1110 displays Au14Ay and .
Input 1111 displays Au15Ay A counter-centric binary-to- binary coded decimal and multiplexed A (Ahmed M.
Elnga.
A ISSN: 1693-6930 The proposed counter-centric multiplexing approach demonstrates several key advantages over recent FPGA-based display drivers as seen in Table 3.
While high-performance systems such as .
achieve 6001100 frames per second (FPS) for micro-LED displays, and .
report 4320 Hz for signage applications, these aggressive refresh rates incur significant power penalties due to the direct proportionality between switching frequency and dynamic power .
cE Oy yceyaycOA).
In contrast, this work targets the minimum refresh rate necessary to eliminate visual flicker .
-120 Hz perceptual threshol.
, achieving 190.
7 Hz while reducing dynamic power by 45% compared to conventional ycA = 16 divider configurations.
Unlike the complex intercross scanning and double-driver architectures employed by .
for 10-bit grayscale control at 2100 Hz, the proposed clock-enable-based controller maintains synchronous timing without clock gating, ensuring robust FPGA design practices with minimal resource utilisation.
Furthermore, while .
demonstrates FPGA-based 6-digit multiplexing for medical applications without specifying refresh parameters, this work provides an explicit analytical timing model .
ceyceycycaycoyce = yceycaycoyco ) that enables predictable design scaling for arbitrary digit .
cAya y 2ycA ) counts and input widths.
The measured flicker-free, ghost-free display operation validates that educational and low-power embedded applications benefit more from optimised refresh rates than from unnecessary highfrequency scanning, positioning this work as a resource-efficient and analytically grounded alternative to existing display multiplexing solutions.
Table 3.
Comparison of recent FPGA display/multiplexing systems Reference .
Method
Block-based control with FPGA
Refresh rate
600-1100 FPS
Not specified 4320 Hz display Enhanced grayscale, reduced .
FPGA-based 6-digit display with Time-multiplexed pulse-width modulation (PWM) with grayscale Intercross scanning with double driver Power/claims High throughput, selective block updates Medical settings application High precision 10-bit grayscale This Counter-centric clock-enable 2100 Hz .
, 300 Hz .
7 Hz frame Reduced dynamic power (POy.
, 45% lower than N=16 Device Micro-LED
FPGA
Xilinx Artix-7
FPGA
LED signage Micro-LED with FPGA control Nexys-4 DDR (Artix-7 FPGA) CONCLUSION We designed, analysed, and validated a modular VHDL architecture that converts a 4-bit binary input to BCD and drives two seven-segment digits on the Nexys-4 DDR using a clock-enableAebased multiplexing The timing model accurately predicted the behaviour observed in simulation and hardware: with ycA = 18 the display refreshes at O191 Hz, which proved both flicker-free and ghost-free, while reducing switching activity compared with conventional high-rate scanning.
The implementation produced correct decimals for all 16 input codes and required only simple counters, a small combinational converter, and a registered segment bus, making it easy to replicate in teaching laboratories and embedded prototypes.
The method generalises cleanly.
The same sizing rule yceframe = yceclk /.
cAya 2ycA ) lets designers choose ycA for any number of digits ycAya and any input width once converted to BCD .
, 8Ae16-bit sources with 3Ae5 Practical next steps include formalising the parameterised BIN2BCD for 8Ae16-bit inputs.
FUNDING INFORMATION
Authors state no funding involved.
AUTHOR CONTRIBUTIONS STATEMENT
This journal uses the Contributor Roles Taxonomy (CRediT) to recognize individual author contributions, reduce authorship disputes, and facilitate collaboration.
Name of Author Ahmed M.
Elngar Muhamad S.
Mauladdawilah Tariq H.
Alomary ue ue ue ue ue ue ue ue ue ue ue ue ue ue ue TELKOMNIKA Telecommun Comput El Control.
Vol.
No.
April 2026: 676-684 ue ue ue ue ue TELKOMNIKA Telecommun Comput El Control C : Conceptualization I : Investigation M : Methodology R : Resources So : Software D : Data Curation Va : Validation O : Writing - Original Draft Fo : Formal analysis E : Writing - Review & Editing CONFLICT OF INTEREST STATEMENT The authors declare no conflict of interest.
Vi : Visualization Su : Supervision P : Project administration Fu : Funding acquisition DATA AVAILABILITY The raw data supporting the conclusions of this article will be made available by the authors upon reasonable request.
REFERENCES