International Journal of Electrical and Computer Engineering (IJECE) Vol.
No.
June 2025, pp.
11x ISSN: 2088-8708.
DOI: 10.
11591/ijece.
pp1-1x Fault tolerant design for 8-bit Dadda multiplier for neural network applications Raji Chandrasekharan1.
Sarappadi Narasimha Prasad2 School of Electronics and Communication Engineering.
REVA University.
Bangalore.
India Department of Electrical and Electronics Engineering.
Manipal Institute of Technology Bengaluru.
Manipal Academy of Higher Education.
Manipal.
India
Article Info
ABSTRACT
Article history:
As digital electronic systems continue to shrink in size, they face increased susceptibility to transient errors, especially in critical applications like neural networks, which are not inherently error-resilient.
Multipliers, fundamental components of neural networks, must be both fault tolerant and efficient.
However, traditional fault free designs consume excessive power and require substantial silicon real estate.
Among existing multiplier architectures, the Dadda multiplier stands out for its speed and efficiency, but it lacks fault tolerance needed for robust neural network applications.
Therefore, there is need to design a power efficient and fault free Dadda multiplier that can address these challenges without significantly increasing power consumption or hardware complexity.
In this paper a solution involving a fault tolerant Dadda multiplier optimized for neural network applications is proposed.
Because of its speed and efficiency when compared to other multipliers Dadda multiplier is used as the base architecture which is designed using carry select adder (CSA) in conjunction with binary to excess one converter to reduce power and complexity.
To enhance fault tolerance, self-repairing full adder is used to implement the CSA.
This allows the system to detect and correct errors, ensuring robust operation in the presence of transient This combination achieves a power efficient, fault tolerant multiplier with a power consumption of 52.
3 mW, reflecting a 3% reduction in power compared to existing designs.
Received Jul 25, 2024 Revised Jan 31, 2025 Accepted Mar 3, 2025 Keywords:
Carry select adder Dadda multiplier Fault tolerant Low power Self-repairing full adder This is an open access article under the CC BY-SA license.
Corresponding Author:
Sarappadi Narasimha Prasad Department of Electrical and Electronics Engineering.
Manipal Institute of Technology Bengaluru.
Manipal Academy of Higher Education Manipal.
Karnataka, 576104.
India Email: sn.
prasad@manipal.
INTRODUCTION
Fault tolerance can be defined as the property which helps a system to continue operating properly even if there are failures in some of the constituent components.
Designs which are fault tolerant enable the systems to operate at a reduced level rather than failing completely if some part of the system fails.
The systems must have the ability to detect the failures and repair them in as much less time as possible.
A significant portion of all hardware defects are transient faults caused by radiation or temperature For any system to be fault tolerant system, self-checking and self-repairing properties are required.
The most commonly used methods to address faults are redundancy schemes: time redundancy, hardware redundancy and information redundancy.
Protection from transient fault is proposed using Time redundancy in .
in which, similar operations are carried out by the clone hardware, in addition to the primary hardware.
Journal homepage: http://ijece.
ISSN: 2088-8708
at different time intervals.
Difference in time interval to the duplicate hardware is implemented by providing delayed clock.
Detection of fault is done by comparing the outputs arriving at different intervals.
performing similar operations at different time intervals an area overhead and cost can be reduced.
Hardware redundancy method more than one hardware is used to produce different outputs.
Outputs of the redundant and the original are compared to determine the faulty or fault free condition.
The major disadvantage is the area overhead incurred .
To detect real time faults information redundancy could be Fault detection in combinational logic can be carried out by using error detection codes or predicted parity bits.
The major drawback of area overhead in hardware redundancy could be overcome by using multiple parity groups .
Various approaches are used to attain fault tolerance but at the cost of power, area and delay.
Thus, by incorporating fault tolerance and a low power design strategy for the fundamental building blocks, the problem of defective systems and power-hungry redundancy schemes will be reduced.
Adders and multipliers are the building blocks of digital circuits as well as neural networks.
make digital systems fault free it is imperative to use fault tolerant adders and multipliers.
The time required for execution of the algorithms is dependent on the multiplication process which is where we require high speed multipliers.
The comparative analysis of delay power performance of various multipliers given in .
shows that there are several architectures to choose balancing power, delay and area.
To implement fault free circuits, multiplier designs which are fault tolerant should be adopted.
This can be achieved using fault tolerant adders to design multipliers.
The Dadda multiplier, which is known for being faster and more efficient, is selected as the base multiplier architecture.
To farther enhance the Dadda multiplier, a carry select adder (CSA) is proposed.
The CSA improves the speed of arithmetic operations by precomputing multiple sums in parallel.
In this design, the CSA uses a binary to excess one converter, which replaces the conventional adders to reduce power consumption and area.
This setup allows overall reduction in hardware complexity while maintaining performance.
To achieve fault tolerance, self-repairing adder is employed in the CSA.
This design approach helps handle single and double faults effectively thus contributing to the reliability of the multiplier and ensuring that errors can be self-corrected.
One of the fastest adder in digital systems is CSA which performs better arithmetic operations.
Using fault tolerant CSA Dadda Multiplier design is proposed here.
The proposed CSA is built using self-repairing full adder which is fault tolerant.
This Dadda multiplier can be used in neural network applications.
RELATED WORK
Many low power implementations of adders using pass transistor logic, transmission gate .
, .
results in output degradation and consumes more power.
Using pass transistor and branch-based logic, full adder design .
can reduce the dynamic power consumed.
Reduced power consumption can be obtained from hybrid full adder using gate diffusion method .
, .
The full adder mentioned in .
which uses 16 transistors is a very promising design for the application outlined in this study since it has low power dissipation and good output fidelity.
To keep the integrity, a hybrid 20-T Full adder that generates full swing at both the sum and carry could be used.
Compact and low power architecture using shared adder .
could be used in implementing CSA.
The CSA adder is regarded as one of the quickest adders for solving arithmetic functions in majority of the digital processing systems .
The propagation of carry to the following step is the primary factor that restricts the speed of addition.
Usage of CSA can be seen in a variety of processing systems to obtain sum by producing a number of carry from which one carry is chosen and hence optimizing the delay issue of carry propagation .
However, the major issue here is that the CSA uses numerous pairs of ripple carry adders (RCA) by seeing carry as input to construct the carry and the respective partial sum.
The final sum and carry are chosen by a multiplexer (MUX), and the entire process shows that this approach is inefficient use of area.
Therefore, a fundamental idea of applying a binary to excess-1 converter (BEC-.
is provided to advance the speed of addition .
Based on the capabilities, the multiplication procedure can help the system to reach a high data rate .
We need high speed multiplier because the majority of the algorithmsAo execution times depend on the multiplication operation.
A huge volume of data must also be evaluated in a variety of applications of digital processing systems and very large-scale integration (VLSI) which calls for high performance processors .
Multipliers are essential in achieving improved performance outcomes for this goal.
Therefore, the multiplierAos operating speed is crucial and must be taken into account when developing circuits for digital systems specially for general-purpose processing .
There have been numerous attempts in recent years to create multipliers that offer high speed and low power.
In essence, multipliers come in two flavors: serial multipliers and parallel multipliers.
In general, parallel multipliers operate more quickly than serial multipliers .
Ae.
Several multipliers like array multipliers.
Dadda multipliers.
Wallace.
Booth multipliers are studied for their performance in .
Ae.
Different algorithms and strategies have already been developed to achieve the least amount of delay, power consumption, and output through a digital Int J Elec & Comp Eng.
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Int J Elec & Comp Eng
ISSN: 2088-8708
Merge delay transform .
, .
, genetic evolutionary algorithms are a few of the strategies now in All of these methods are implemented using complementary metal-oxide-semiconductor (CMOS) Low power design approaches for other applications for VLSI implementation discussed in .
Ae.
is studied to see whether those can be applied for the application tried here.
There are three steps in the operation of multipliers: creation of a partial product, its addition, and its final addition.
The second stage of multiplication often involves the partial product reduction process, which can be bottleneck in terms of performance and power consumption.
Parallel prefix adders, approximate adders, novel compressors are some of the methods reviewed in .
Dadda multiplier designed using compressors are discussed in .
shows considerable prospects in reducing area and power and delay.
A non-truncated design is used to design Wallace multiplier in .
using approximate compressors which shows increased performance and less power consumption.
Applications of approximate compressors for multipliers used for image processing discussed in .
is prospective design as the accuracy metric is not compromised and has less power In multiplier design as discussed in .
uses an and gate to generate a correction term to correct errors.
Approximation method for multiplication using 4:2 compressors and full adders is discussed for image processing applications in .
Approximate computing assessment techniques for internet of things (IoT) and machine learning applications where requirement for accuracy is not paramount is discussed in .
Recursive based approximate multipliers for error resilient application is discussed in .
which is a prospective contender in low power applications.
In the existing architecture, it is found that different multipliers are build using full adder which are not fault free.
In order to overcome this problem.
Dadda multiplier is implemented using CSA which is fault tolerant with low power implementation.
PROPOSED DESIGN
Proposed fault tolerant carry select adder The multiply accumulate unit (MAC) consists of adders, multipliers and accumulators where the multiplier is the heart of every MAC unit.
The reduction and generation of partial product in multipliers has large contribution to power consumption.
A regular CSA includes two RCA which produces sum and carry.
One RCA generates AoCarry 0Ao and the second RCA generates AoCarry 1Ao.
Multiplexers are used for the selection of any one carry pin output.
But the carry select adder-based Radix-multiplier consumes larger area and more number of transistors.
To avoid more power consumption fault tolerant CSA using binary to excess one converter (BEC-.
is implemented.
The constituent fault tolerant self-repairing full adder .
block as shown in Figure 1 is used in CSA in turn making the CSA fault free.
For the sake of brevity 4-bit adder design is considered here.
Figure 2 represents the block diagram of fault tolerant CSA.
Here carry 1 operates the same as that of regular CSA but carry 0 makes use of BEC-1 that adds 1 carry in the sum.
Finally.
MUX used to select the end result based on actual carry Cin.
Equations .
represent the sum and the carry out for the fault tolerant 4-bit carry select adder.
ycIycn = .
cUycn O yaycnycu ) .
cUycuycn O yaycnyc.
yaycuycyc = .
a4 O yaycnycu ) .
cUycu3 O yaycnyc.
Figure 1.
Block diagram of self-repairing full adder consisting of self-checking full adder which identifies fault and a decision-making MUX .
Fault tolerant design for 8-bit Dadda multiplier for neural network applications (Raji Chandrasekhara.
A ISSN: 2088-8708 Figure 2.
Block representation of 4-bit carry select adder using binary to excess 1 converter, full adder and 2:1 MUX .
Proposed Dadda multiplier Dadda multiplier works similar to that of Wallace tree multiplier, but the difference is it is much faster and requires fewer gates.
The proposed carry select adder is implemented in Dadda multiplier to obtain low power.
Figure 3 represents the dot diagram of 8-bit Dadda multiplier where the height of each stage depends on the working principle of the final stage.
The final stage includes two partial product rows.
Each stage has a height of order 2, 3, 4,6,9,13,19,28,42,63.
The complete 8-bit dot diagram includes six stages.
This stage includes 16 number of rows.
Figure 3.
Dot diagram of Dadda multiplier for N=8 The first stage involves simple multiplication of multiplicand and multiplier which is termed as partial product stage.
The first column in first row represents the least significant bit.
2 nd row stage is being obtained from 3rd row stage, and 3rd row stage is obtained from 4th row stage with the help of .
, .
, .
counters from the dot diagram.
S indicated the number of stages used to implement the multiplier.
In the Int J Elec & Comp Eng.
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ISSN: 2088-8708
(S-.
stage,6th row stage helps in deriving the 4th row stage.
The 6th row can be obtained from 9th row stage.
This can be (S-.
th stage.
In the (S-.
stage, the 9th row stage is gained by 13th row and it can be obtained from partial product stage.
The needed number of full adders in this Dadda implementation is N2-4N 3, and required number of half adders is N-1.
Figure 3 shows the total number of reduced stages to design Dadda For clarity 4-bit multiplier operation is shown here.
8-bit operation can be obtained by using two of such 4-bit blocks.
Figure 4 represents the block diagram of 4-bit Dadda multiplier.
Figure 4.
Block diagram representation of Dadda multiplier using carry select adder implemented using the design mentioned in Figure 2
RESULTS AND DISCUSSION
The proposed Dadda multiplier is designed using ISE Xilinx software and the waveform is simulated using Xilinx simulator.
Figure 5 represents the simulation results of fault tolerant self-repairing full The faults occurred in the full-added circuit is repaired by the self-repairing process.
Figure 6 represent schematic diagram of 4-bit fault tolerant carry select adder using excess 1 convertor where there are 4 bits of input AoAAo and 4 bits of input AoBAo along with Cycnycu and Cycnycu 0.
It produces an output of sum S0 Ae S3 and carryout Cycuycyc.
Figure 7 represents RTL schematics view of 4-bit fault tolerant carry select adder obtained after synthesizing the code.
Figure 8 shows simulation waveform of 4-bit fault tolerant carry select adder.
The inputs are Ao Ae A3 and Bo Ae B3.
Outputs Sum is represented as S0 Ae S3 while the carry is represented as Cout.
Figure 5.
Simulation results of self-repairing full adder Fault tolerant design for 8-bit Dadda multiplier for neural network applications (Raji Chandrasekhara.
A ISSN: 2088-8708 Figure 6.
Top level schematic diagram of 4-bit fault tolerant carry select adder Figure 7.
RTL Schematic view of 4-bit fault tolerant carry select adder Figure 8.
Simulation result of 4-bit fault tolerant carry select adder Int J Elec & Comp Eng.
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8-bit Dadda multiplier can be made by extending the 4-bit design discussed previously.
The 8-bit Dadda multiplier which is implemented using fault tolerant CSA with BEC.
It includes 8 bits input of A and B and produces a final output of 16-bit.
Figure 9 shows the RTL Schematic view and Figure 10 represents simulated waveform of 8-bit Dadda For different values inputs the results are verified.
Table 1 shows comparative result for power and delay of 8-bit Wallace.
Array and Dadda multiplier.
The comparison results show that among all the multipliers Dadda multiplier with CSA using excess one converter in its carry propagation path is more efficient.
The power is reduced by 3% when compared to Wallace Tree multiplier and the delay is reduced by 2.
Figure 9.
RTL schematic view of 8-bit Dadda multiplier Figure 10.
Simulation result of 8-bit Dadda multiplier Table 1.
Comparison of different multipliers based on delay and power dissipation Multipliers .
Array multiplier Wallace multiplier Dadda multiplier Delay .
Power .
W) CONCLUSION Neural networks are not inherently fault tolerant.
It has to be made fault free.
Implementations of fault free carry select adder and multiplier can result in the constituents of a neural network fault free.
The Self-Repairing full adder design can identify and repair both single and double faults at a time.
The aim of fault-tolerant circuits is to reduce the probability of failures.
The constituent self-repairing full adder which is used for CSA is fault tolerant in nature.
Since this is used for building CSA, in turn making it fault free.
8-bit Dadda multiplier which has low power dissipation is implemented using this CSA.
The desired output waveforms are obtained.
In this paper, an implementation of the Dadda multiplier is carried out.
The Power consumed by the proposed Dadda multiplier is 5.
23 mW.
The power comparison results show that the proposed design reduces the power by 3% than array multiplier and wallace multiplier.
CSA with BEC that is fault tolerant is designed and implemented in the proposed multiplier.
From all the comparison results it is evident that the Dadda multiplier using fault tolerant CSA with BEC more efficient.
The proposed 8-bit Dadda tree multiplier which uses the fault-tolerant CSA using BEC-1 reduces power significantly more than several other existing multipliers.
These multipliers, though, are also fairly quick compared to other Fault tolerant design for 8-bit Dadda multiplier for neural network applications (Raji Chandrasekhara.
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ACKNOWLEDGEMENTS
The authors acknowledge the support from REVA University for the facilities provided to carry out the research.
FUNDING INFORMATION
Authors state no funding involved.
AUTHOR CONTRIBUTIONS STATEMENT
This journal uses the Contributor Roles Taxonomy (CRediT) to recognize individual author contributions, reduce authorship disputes, and facilitate collaboration.
Name of Author Raji Chandrasekharan Sarapadi Narasimha Prasad C : Conceptualization M : Methodology So : Software Va : Validation Fo : Formal analysis ue ue ue ue ue ue ue ue ue I : Investigation R : Resources D : Data Curation O : Writing - Original Draft E : Writing - Review & Editing ue ue ue ue ue ue ue Vi : Visualization Su : Supervision P : Project administration Fu : Funding acquisition CONFLICT OF INTEREST STATEMENT Authors state no conflict of interest.
DATA AVAILABILITY
Data availability is not applicable to this paper as no new data were created or analyzed in this study.
REFERENCES