International Journal of Electrical and Computer Engineering (IJECE) Vol.
No.
August 2017, pp.
ISSN: 2088-8708.
DOI: 10.
11591/ijece.
TCAD Simulations and Small Signal Modeling of DMG AlGaN/GaN HFET Rahis Kumar Yadav.
Pankaj Pathak.
R M Mehra Department of Electronics and Communication Engineering.
School of Engineering and Technology.
Sharda University.
Knowledge Park- i.
Greater Noida.
Uttar Pradesh, 201306.
India
Article Info
ABSTRACT
Article history:
This article presents extraction of small signal model parameters and TCAD simulation of novel asymmetric field plated dual material gate AlGaN/GaN HFET first time.
Small signal model is essential for design of LNA and microwave electronic circuit by using the proposed superior performance HFET structure.
Superior performances of device are due to its dual material gate structure and field plate that can provide better electric field uniformity, suppression of short channel effects and improvement in carrier transport In this article we used direct parameter extraction methodology in which S-parameters of device were measured using pinchoff cold FET The measured S-parameters are then transformed into Y-parameters to extract capacitive elements and then in to Z-parameters to extract series parasitic elements.
Intrinsic parameters are extracted from Y-parameters after de-embedding all parasitic elements of devce.
Microwave figure of merits and dc performance are also studied for proposed HFET.
The important figure of merits of device reported in the paper include transconductance, drain conductance, current gain, transducer power gain, available power gain, maximum stable gain, maximum frequency of oscillation, cut-off frequency, stability factor and time delay.
Reported results are valdated with experimental and simulation results for consistency accuracy.
Received Feb 24, 2017 Revised Apr 28, 2017 Accepted May 27, 2017 Keyword:
Cutoff frequency HEMT model Microwave figure of merits Parameters extraction Small signal model Copyright A 2017 Institute of Advanced Engineering and Science.
All rights reserved.
Corresponding Author:
Rahis Kumar Yadav.
Departement of Electronics and Communication Engineering.
Sharda University.
Knowledge Park-i.
Graeter Noida.
Gautam Buddha Nagar.
Uttar Pradesh, 201306.
India.
Email:rahiskumaryadav@gmail.
INTRODUCTION
Due to unique properties of GaN material, it is possible to obtain large current densities in GaNbased HFETs .
, .
GaN based devices are also very useful for high frequency high temperature microwave applications such as radar systems .
, .
In the recent past, studies have been done on asymmetric MOSFETs .
, junctionless FETs .
and dual material gate AlGaAs/GaAs HEMTs structures that uses two metals of different work functions .
Since analytical models help us to understand internal solid state device physics thus expected to be consistent with physical behavior of device.
An accurate small signal model of HFET is extremely valuable for designing of important active circuits generally used for high frequency applications .
These small signal compact models define physical characteristics and various limitations of active devices accurately .
, thus used for design of low noise power amplifiers by electronics and microwave engineers in industry.
Small signal models of advanced devices are needed for CAD based simulations .
for analysis and validation of newly developed device structures .
In present scenario, analytical models are much exploited for getting true feedback about optimization of fabrication process in semiconductor industries .
, .
In past most of small signal models developed for conventional HEMT structures are based on various approaches of device modelling .
, .
One of initial kind of detailed small signal Journal homepage: http://iaesjournal.
com/online/index.
php/IJECE A ISSN: 2088-8708 model that describe extraction procedure of FET structures, was proposed in 1988 by Dambrine, et al .
recent past many researchers have developed variety of techniques and methods according to their used material system and conventional device structures .
, .
Requirement for development of small signal model for DMG AlGaN/GaN HEMT structure is felt since long but no such model for enhanced device structure is reported in recent past.
In this paper we proposed small signal model for DMG GaN HFET structure incorporating field plate that can be exploited for advanced microwave circuit designs and for CAD based simulations.
It is possible to classify some existing modeling methods in three broad categories: whole optimization, partial optimization .
and direct extraction methods .
, .
For the propoed DMG AlGaN/GaN HFET, the direct parameter extraction approach is used as it provides better consistency between parameter values and physical structure of device.
This approach also facilitates extraction process to run faster than other techniques described earlier.
Extraction is carried out using low as well as higher frequency as cold FET structure thus assures higher extraction accuracy .
Extracted small signal model parameters and dc as well as ac simulation results can provide clear insight about use of proposed device for microwave ranges of frequencies.
DEVICE STRUCTURE AND MODEL FORMULATION
Device Structure for Parameter Extraction and TCAD Simulations Self explanatory schematic view of device structure of dual channel dual material gate Al 0.
3Ga0.
GaN HFET is shown in Figure 1.
In the proposed unique device the dual material concepts are based on previously fabricated devices by W.
Long et al.
Epitaxial layers of HFET were grown by MOCVD on a 5-inch sapphire substrate.
Drain and source terminal ohmic contacts were formed by Ti/Al/Ni/Au metal stacks, followed by rapid thermal annealing at 884AC for 50 seconds in nitrogen environment.
Dual material gate was e-beam defined keeping total gate length of 1AAm.
Ni/Au metallization process was used to form dual metal gate Schottky contacts with the AlGaN cap layer.
A Si3N4 surface passivation layer was deposited using PECVD.
In order to reduce source inductance via-holes were formed using plasma dry etching.
Field plate is formed to increase E-field uniformity that further reduces current collapse in device (Li, et al.
, 2.
For completing the fabrication process of the device using 100AAm2 gate area a standard gold plated air brdge process was used.
Metals M1 (A.
and M2 (N.
having work functions iM1(=5.
3eV) and iM2 (=4.
eV) respectively define dual metal gate with width W (=100yy.
for the device.
A 3nm AlGaN cap layer forms interface between n-Al0.
3Ga0.
7N layer of 18 nm thickness that is followed by UID AlGaN spacer layer of 3 nm thickness.
Purpose of introducing UID AlGaN spacer layer is to reduce ionized impurity scattering.
A 2m thick GaN channel layer is used to form heterointerface that creates 2-DEG conductive channel in the Sapphire substrate is used for device structure as it can withstand higher operating temperature as a power switching device.
Figure 1.
Cross sectional schematic of enhanced asymmetric DMG Al0.
3Ga0.
7N/GaN HFET .
Small signal equivalent circuit model Analytical Small Signal Circuit Mode Description Figure 1.
represents small signal equivalent circuit model for the proposed unique device Rg.
Rs and Rd represent parasitic resistances of gate, source and drain respectively.
Ls.
Ld.
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represent source, drain and gate electrodes inductances respectively.
Cpd.
Cpg, and Cpgd, represent device contact pad capacitances between drain-source, gate-source and gate drain respectively.
Cpdi.
Cpgdi, and Cpgi are inter-electrodes capacitances between drain-source, gate-drain and gate-source respectively.
Rgs and Rgd represent input and output channel region resistances.
C ds.
Cgs, and Cgd, represent intrinsic capacitances between drain-source, gate-source and gate-drain respectively.
gds and gm represents drain conductance and transconductance of device.
The gmVgs in small signal model represent current generator in the output circuit, where Vgs represents as gate to source voltage with a phase shift of e -jOE.
Symbol (E) represents transit time through the velocity saturated region of the 2DEG-channel.
The O is angular frequency .
ad/se.
of the applied RF signal at gate terminal of device.
Method for Parameter Extraction Parameter extraction is performed by using direct method as suggested by Minasian .
and later modified by Dambrine et al .
and Berroth and Bosch .
Initially S-parameter extraction is carried out for shunt extrinsic elements of device under pinch off mode of biasing keeping frequency with in 5GHz range thre after for series elements at higher frequency range.
These measured S-parameters are then successively transformed into Y-parameters and then in to Z-parameters in order to obtain values of all the shunt and series parasitic elements.
Again after de-embedding of all the parasitic elements, the intrinsic Yparameters are obtained.
At the end intrinsic elements are derived by separating real and imaginary parts of intrinsic Y-parameters.
Extrinsic Parameters Extraction and Analytical Expressions The extrinsic capacitive elements are extracted from imaginary Y-parameters under pinch-off condition (Vgs < Vpinch-off and Vds=0V).
Now the equivalent voltage controlled current source forming intrinsic part of device is disabled.
In case of low frequency input in the range of 5 GHz, the whole circuit can be treated as a capacitive network as shown in Figure 2.
Following Equations can appropriately describe the relationship between extrinsic capacitances and imaginary parts of the Y-parameters under pinched off Im AY11 A A jA C pg A Cgsi A Cgsp A Cgdp A Cgdi A C pgd Im AY12 A A Im AY21 A A A jA(Cgdp A Cgdi A C pgd ) A Im AY22 A A jA Cdsp A C pd A Cdsi A Cgdp A Cgdi A C pgd In Figure 2.
imaginary Y-parameter curves with in frequency range of 5GHz are shown.
It is clear that Y-parameters have sufficient linearity at low frequency range .
elow 5GH.
Therefore, the parasitic capacitances can be safely extracted from the slop of imaginary Y-parameter curves.
Here.
Cgsp.
Cgdp and Cdsp provide intrinsic substitute of pinched of cold FET part of circuit.
Assumption is made as .
Cdsp A 12C pd Due to asymmetric device structure ratio of gate-drain spacing with that of gate-source spacing is 1.
So the relationship of its capacitance can be expressed as Cgsp A 1.
5Cgdp Since size and shape of all pads are same so these capacitances can be treated as equal in value as C pg A C pd A C pgd Considering device structure Cdsi is larger than pad capacitances.
An assumption is made here as Cgdp A Cgdi TCAD Simulations and Small Signal Modeling of DMG AlGaN/GaN HFET (Rahis Kumar Yada.
A ISSN: 2088-8708 Under high frequency small input signal with gate forward biased (V gsOu.
drain at zero potential (Vds=0V), small signal equivalent circuit is reduced as in Figure 3.
In this condition gate leakage current (I.
flows and internal device capacitances are shunted with conductance open circuited.
Since all inter electrodes capacitances are inside of parasitic resistance so no approximation needed by keeping precision of compact model as intact.
At this specific bias point, the following simplified Equations of Z-parameters are Z11 A Rs A Rg A Rc A KT A jA Ls A Lg A A 1 A r qI g jACgf jACsf Z12 A Z 21 A Rs A A A .
A jA Ls A jACsf Z 22 A Rs A Rd A Rc A jA A Ls A Ld A A A jACdf jACsf Figure 2.
Reduced equivalent circuit under low frequency cold FET pinchoff condition .
Imaginary Yparameters versus frequency plot In the above expressions.
Rc, represents channel resistance and r represents ratio of channel resistance between gate to drain and gate to source i.
=Rcgd/ Rcg.
As per our proposed asymmetric device structure value of r is 1.
5 considering source and drain separation from gate.
Cdf.
Cgf and Csf, represent fringing capacitances resulting at drain, gate and source terminals respectively in cold FET high frequency equivalent circuit.
Also AkT/qIg in Equation .
gives the differential resistance of the Schottky diode.
In this expression.
K and T represent ideality factor of diode.
Boltzmann constant and absolute ambient temperature respectively.
Now by transforming Y-parameters in to Z-parameters.
Rg.
Rs and Rd can be extracted from the Re (Zi.
By multiplying O by imaginary parts of impedances, following expressions are obtained Im(A Z11 ) A A 2 ( Ls A Lg ) A Im(A Z12 ) A A 2 Ls A A Cgf Csf Csf Im(A Z 22 ) A A 2 ( Ls A Ld ) A .
A Cdf Csf IJECE Vol.
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The OIm(Zi.
versus O2 plot is shown in Figure 3.
Slop of these curves can be used to extract values of Lg.
Ld and Ls respectively.
The imaginary part of the Z-parameters increases linearly with frequency but real part is independent from frequency variations.
The value of R c is determined by forming following Equations by using pinch off Z-parameters as follows Re(Z22 pinch-off ) A Rs A Rd Also, from Equation .
it is noted that Re(Z22 ) A Rc A Rd A Rc Rc A Re(Z22 ) A Re(Z22 pinch-off ) .
Intrinsic Parameters Extraction and Analytical Expressions The intrinsic part of the device can be described by the following Y-parameters:
Y11int A A 2Cgs 2 Rgs
Y12int A A A A 2Cgd 2 Rgd
E Cgs Cgd E
A jA E
A E
E A
A 2Cgd 2 Rgd
Cgd
A jA
A 2Cgd 2 Rgd
Cgd
A jA
A 2Cgd 2 Rgd
Cgd E
A jA E Cds A E
A E
Y21int A g m eA jAA A Y22int A g ds A .
A A 1A u2 u A ACgs Rgs A A 1 A v2 v A ACgd Rgd Therefore, the value of individual intrinsic parameter can be derived from Equations .
by separating real and imaginary parts of Y11int.
Y12int.
Y21int and Y22int and using following expressions Cgd A A.
A v 2 ) R gd = A .
v 2 )Im AY12int A Cgs A .
A u 2 ) Rgs A Im(Y12int ) .
Im AY11int A A Im AY12int A A Im AY11int A Y12int A 1A u2 TCAD Simulations and Small Signal Modeling of DMG AlGaN/GaN HFET (Rahis Kumar Yada.
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gm A Y21int A Y12int
A AA
Cds A .
E Im AY21int A Y12int A E E Re AY A Y A EE Im AY22int A Y12int A .
A gds A Re AY22int A Y12int A .
Figure 3.
Reduced cold FET high frequency equivalent circuit under forward gate bias (Vgs>.
OIm (Zi.
versus O2 plot Extrinsic parameters as listed in Table 1, are extracted for 1x100AAm2 gate size device at ambient temperature (T) =305K.
The capacitances are extracted for fL=0 to 5GHz.
Vgs= -8V.
Vds=0V.
For series inductances and resistances, fH=5 to 200GHz.
Vgs = -3V.
Vds=0V is applied.
Intrinsic parameters as listed in Table 2, are extracted from S-parameters measured at Vds=10V and Vgs= -1V.
T=305K, fH=5 to 200 GHz.
These parameters are also validated with recently reported results .
Table 1.
Extracted extrinsic parameters of small signal circuit model Extrinsic Parameters Value Cpg Cpd Cpgd Cdsi Cgsi Cgdi Table 2.
Extracted intrinsic parameters of small signal circuit model Intrinsic Parameter Value Cgd Cgs Cds Rgd Rgs 500mS/mm 800mS/mm Characterization and Modelling of Microwave Figures of Merits Microwave performance of device was characterized using Agilent Technologies N5230A network The system calibration ensured with a short-open load-through calibration standard.
Figure 4 shows block diagram for extraction of S-parameters by using two port matching lossless output and input network.
Circuit shows Es.
Zs and ZL as excitation source, source impedance and load impedances respectively.
P i .
PA.
PL and Pavo represent input power, available input power, power delivered to load and available power at output respectively.
Paper models following figure of merits for proposed unique device P Transducer power gain (GTP) IJECE Vol.
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GTP A
For S12=0 values unilateral transducer power gain (GUTP) is obtained as GUTP A PAS12 A 0 Available power gain (GAP) GAP A Pavo Since PavoO PA, thus power gain GAP OuGTP Maximum available gain (GMAX) occurs for the simultaneous conjugate match at the input and output port if the transistor is unconditionally stable i.
and given as S21
GMAX A
S12
Ak C k A1A
Where k represents stability factor of device and obtained as kA
1 A S11 S22 A S21S12 A S11 A S22
2 S12 S21
Maximum stable gain (GMS) occurs when the two port are resistively loaded till stability factor becomes unity .
= .
GMAX of the two port of Equation .
becomes maximum stable gain and obtained as GMS A S21
S12
Maximum unilateral transducer power gain (GUTPM) is obtained when the transistor becomes unconditionally stable and obtained as GUTPM A S21
A1- S AA1- S A
Maximum unilateral power gain (GUPM) is largest gain and obtained as GUPM A 1 S21
2 S12
ES E
k 21 A Re E 21 E
S12
E S12 E
Current gai.
is important and used to obtain cut off frequency of device H 21 A 2S12 A S11 ).
A S22 ) A S12 S21
Cut off frequency .
for DCDMG AlGaN HEMT at which short circuit current gain rolls off to 0 dB can be obtained as TCAD Simulations and Small Signal Modeling of DMG AlGaN/GaN HFET (Rahis Kumar Yada.
A ISSN: 2088-8708 ft A 2A (Cgs A Cgd ).
A A Rs A Rd A gds ] A Cgd gm ( Rs A Rd ) .
Maximum oscillation frequency .
can be determined by using intrinsic and extrinsic components of device as f max A 2 (( Rg A Rs A Rgs ) g ds A 2A f t Cgd Rg ) .
Figure 4.
Block diagram of matching impedance network for s-parameters measurement RESULTS AND DISCUSSIONS We used MATLAB and Silvaco TCAD ISE .
as modeling and device simulation tools respectively for our research work.
GaN material based device models .
rint srh, albrct.
and polarization based models are applied for considering piezoelectric and spontaneous polarization effects at the heterointerface of the GaN device structure as described in ATLAS user manual of Sivaco TCAD.
Figure 5.
shows comparison of simulated .
and experimental .
output current voltage characteristics of device for various gate-to-source voltages (Vg.
Figure 5.
shows comparison of simulated and experimental .
input characteristics of DMG AlGaN/GaN HFET.
It is evident from graph that gate has effective control on drain current in DE mode of operation.
The device stability analysis has been done with the help of Smith plots.
Figure 6.
shows model and measured s-parameters .
Smith plots analysis reveals that proposed device capacitance increases with At the lowest input frequency the input reflection coefficient, i.
S11= 1, represents maximum reflection and open circuit.
With the rise in frequency the input reflection coefficient moves towards clockwise direction in the circle of capacitance and approaches to the matching point at S 11=0.
Since, at the matching point no reflections would occur because of the impedance matching and this confirms good performance of device at higher frequency range.
Similarily output reflection coefficient S22 moves from maximum reflection to minimum reflection towards matching point in the circle of capacitances.
Graphs also depicts that with rise in frequency, both the transmission coefficients (S.
and (S.
move towards clockwise direction in the circle of inductances assuring good performance of device at microwave frequency Figure 5.
Output current voltage (Id-Vd.
characteristics simulated .
ashed lines with symbol.
olid lines symbol.
Transfer (Id-Vg.
characteristics curve IJECE Vol.
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The device simulation and measured gains .
, .
are plotted as a function of frequency at a gate bias of Vgs=-1V in Figure 6.
On comparison the results and found to be within close conformity thus validating device performance in microwave frequency range.
Graph clearly demonstrates that the gains decrease with the rise in frequency and the cut-off frequency .
occurs at 68 GHz and maximum oscillation .
occurs at 178GHz.
In Figure 7.
, the variation of capacitances i.
Cgd.
Cgs.
Cgg and Cds are demonstrated with the rise in frequency.
It clealy shown that capacitance values remain almost constant up to 200GHz frequency range that is covering maximum oscillation frequency of device.
Figure 7.
demonstrates the simulated and experimental variation of cutoff frequency with Vgs at the Vds=24 V.
Figure 8 shows variation of simulated and experimental transconductance with Vgs.
Comparison of simulation and experimental results .
validate device suitability for microwave range of frequency.
Figure 6.
S-parameters (S11.
S12.
S21 and S.
plot on smith chart, simulated .
ashed blue line.
olid red line.
at bias Vds=24V and Vgs= -1V, frequency fstart=1GHz and fstop=200 GHz .
Gains versus frequency plot for Vds=24V and Vgs= -1V.
Figure 7 .
Capacitances versus frequency plot model .
ashed lines with circle.
olid lines with diamond.
at Vds=5V and Vgs= -1V .
Cutoff frequency versus Vgs plot, simulation .
olid line with diamond.
ashed line with circle.
at Vds=5V Figure 8 Transconductance .
versus gate to source voltage (Vg.
TCAD Simulations and Small Signal Modeling of DMG AlGaN/GaN HFET (Rahis Kumar Yada.
A ISSN: 2088-8708
CONCLUSION
Finally it can be concluded that the extracted small signal model parameters of dual material gate Al0.
3Ga0.
7N /GaN HFET structure are accurate and predict proposed device suitability for LNA that can operate in microwave range of frequencies.
Device structure is simulated for analysis of transfer characteristics, output current voltage characteristics and microwave figure of merits.
Simulated results are compared with experimental data to analyze device performance and behavior under dc biasing.
We obtained maximum oscillation frequency .
of 178 GHz and cut-off frequency .
of 68 GHz as enhanced device Important figure of merits analysed and reported in the article include current gain |H.
, transducer power gain (GTP), unilateral transducer power gain (GUTP), maximum stable gain (GMS), maximum available gain (GMAX), transconductance .
, drain conductance .
, stern stability factor .
, available power gain (GAP) and time delay (E) to assess microwave performance of proposed device.
Extracted parameters are validated for consistency and accuracy with experimental results and found to be in close conformity.
REFERENCES