International Journal of Electrical and Computer Engineering (IJECE) Vol.
No.
June 2014, pp.
ISSN: 2088-8708
Realization of Programmable BPSK Demodulator-Bit Synchronizer using Multirate Processing Anshuman Sharma*.
Abdul Hafeez Syed.
Midhun M.
MR Raghavendra Spacecraft Checkout Group.
ISRO Satellite Centre Bangalore, 560017.
India
Article Info
ABSTRACT
Article history:
This paper presents the design and implementation of programmable BPSK demodulator and bit synchronizer.
The demodulator is based on the Costas loop design whereas the bit synchronizer is based on Gardner timing error The advantage of this design is that it offers programmability using multi-rate processing and does not rely on computation of filter coefficients.
NCO angle input for each specific data rate and thus avoids computational The algorithm and its application were verified on MatlabSimulink and was implemented on ALTERA platform.
A 32 kHz BPSK demodulatorAebit synchronizer pair catering for data rates from 1 kbps to 8 kbps was implemented.
Received Jan 2, 2014 Revised May 4, 2014 Accepted May 24, 2014 Keyword:
BPSK
Costas loop
FPGA
Gardner Timing Detector
VHDL
Copyright A 2014 Institute of Advanced Engineering and Science.
All rights reserved.
Corresponding Author:
Anshuman Sharma.
Spacecraft Checkout Group.
ISRO Satellite Centre Bangalore, 560017.
India Email: anshuman@isac.
INTRODUCTION
Bipolar phase shift keying (BPSK) modulation is widely used modulation scheme in telemetry chain of satellites due to its power efiiciency.
The modulation scheme employed for telemetry transmission is PCM/PSK/PM.
Whereas the PM modulation is done at S-band/C-band frequencies, the PSK subcarriers are basically at 32 kHz and 128 kHz.
With the ever increasing complex interplanetary mission being explored by ISRO the telemetry data rates have varied from 100 bps to 8 kbps on the subcarriers.
This work discusses about an implementation scheme of programmable BPSK demodulator-bit synchronizer pair in digital domain which can be dynamically configured for variable data rates.
The BPSK demodulator is Costas loop based design.
The block diagram of Costas loop is given in Figure 1.
There are existing solutions for implementation of BPSK modem .
, .
, .
, .
The Costas loop extracts the demodulated signal at the Auin-phaseAy branch of the loop.
The Numerically controlled Oscillator (NCO) which can be implemented using the Co-ordinate Rotation Digital Computer (CORDIC) algorith.
locks on to incoming signal and simultaneously generates the demodulated output.
The output of the demodulator is given to bit synchronizer for clock recovery, data extraction.
The bit synchronizer can be implemented using the Gardner timing-error detector .
To introduce programmability in this design the arm filters, loop filters and NCOs have to be tuned as per the data rates.
The tunable filters have been discussed in .
All this retuning calls for a computer interface where new filter coefficients.
NCO angle input can be recomputed and passed on to the FPGA design.
Journal homepage: http://iaesjournal.
com/online/index.
php/IJECE A ISSN: 2088-8708 Figure 1.
Basic Costas Loop In this work, we use multirate sampling .
to configure the demodulator-bit synchronizer pair for any data rate from 1 kbps to 8 kbps.
This approach is based on the concept of achieving reconfigurability by varying the sampling frequency rather than recomputing coefficients for reconfiguring.
In the next section we discuss the basic concept and design of the demodulator-bit synchronizer pair.
Subsequently we present the implementation of the design on hardware.
RESEARCH METHOD
The Concept As explained earlier the focus of this work is to achieve programmability without repeatitive computational burdens while designing a programmable BPSK demodulator-bit synchronizer.
The whole concept is based on the fact that in digital signal processing (DSP) all the computations are based on sampling frequency.
A filter working at sampling frequency f1 with passband frequency of fpass and stop band frequency of fstop can be made to work as filter with a different passband and stopband frequency just by changing the sampling frequency to f2, since both fpass and fstop are normalized wrt sampling frequency.
As an example refer to the table 1, a 16 tap FIR filter is designed using Kaiser window for 6-dB pass band frequency of 10 kHz at a sampling rate of 100 kHz.
The ratio of pass band to sampling frequency is 0.
Next the same coefficients are sampled at a rate of 80 kHz and they provide 6-dB pass band frequency of 8 kHz again the same ratio of 0.
1 is maintained.
This concept forms the basis of this work and it has been further discussed.
Table 1.
Filter characteristics wrt sampling frequency Similarly the NCO can be modified to give output at different frequency by simple variation of sampling frequency.
Thus, changing the sampling frequency avoids re-computation of filter coefficients and NCO angle input for varying data rates.
Figure 2 depicts general phase lock loop (PLL) architecture in digital domain.
In the PLL if the loop filter characteristics are to be changed it can be done by two ways- either by recomputation of filter coefficients or as stated above, by changing the sampling frequency.
But changing the sampling frequency IJECE Vol.
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will change the free running frequency of the NCO and changing coefficients require re-computation.
So a new architecture for PLL was thought as depicted in figure 3.
The first NCO-multiplier pair downconverts the input signal to close to zero frequency and the PLL thereafter corrects for the phase and frequency errors.
The loop filter characteristics can be easily modified by changing the sampling frequency.
This change in sampling frequency does not change the output frequency of the second NCO as it is configured to work at zero frequency.
This work demonstrates this concept on FPGA hardware which is discussed in subsequent Figure 2.
Phase lock loop Figure 3.
Modified Phase lock loop Implementation Clock Generation To formulate the concept we did the functional simulation on MATLAB-Simulink and implemented the programmable BPSK demodulator-bit synchronizer pair on an Altera FPGA.
The basic block diagram is presented in Figures 5, 8 and 9.
The design is based on PLL.
Refer to table 2.
the input sampling frequency is 224 kHz.
For the data rates from 8 kbps to 1 kbps the sampling frequency is scaled down from 112 kHz to 14 kHz.
The corresponding interpolation and decimation values are indicated.
All along, the ratio of sampling frequency to data rate is maintained as 14 to provide sufficient samples for bit synchronizer to lock.
Even though bit synchronizer is based on Gardner timing detector which requires only two samples per bit we are taking 14 samples per bit as we are not adjusting our sampling instants but rather selecting the sample pair which gives the best Signal to Noise ratio.
So, sufficient number of samples is required for getting the best strobing instant.
For 8 kbps data rate the sampling rate after interpolation is 1.
792 MHz.
The maximum clock frequency corresponding to this sampling frequency is 32.
256 MHz.
This clock frequency is required for the anti-aliasing filter in between the interpolator and the decimator, refer to figure 5.
The filter is a 64 tap.
Kaiser window FIR filter.
It has been implemented with certain amount of parallelism so clock frequency of 16 times as compared to the sampling frequency is required.
We have kept two clock cycles as buffer, .
256/1.
This clock is generated by an onboard Crystal oscillator.
All the clocks required for programmability are generated by onboard PLL on the FPGA, routed to multiplexer to which selection is provided through input/output (I/O) lines of the FPGA, as indicated in Figure 4.
Realization of Programmable BPSK Demodulator-Bit Synchronizer using Multirate A (Anshuman Sharm.
A ISSN: 2088-8708 Table 2.
Data rates and the clock requirement Figure 4.
Clock generation on FPGA Building blocks Refer to the figure 5, the incoming 32 kHz BPSK modulated signal in the form of ICos( .
(I is the modulating NRZ-M bipolar dat.
is passed through an Anti-aliasing filter(AAF) which is a 6th order Butterworth filter providing necessary rejection at .
sampling frequency/2.
The analog signal is converted to digital signal with sampling frequency .
of 224 kHz using a 10-bit pipelined (ADC) analog to digital This signal is then brought down to close to Au0Ay intermediate frequency (IF) in the form of ICos(AE.
and ISin(AE.
( AEx is the instantaneous phase and frequency error between the between the incoming signal and the NCO) by the front end IQ detector implemented in digital domain using NCO .
unning at sampling frequency of 224 kH.
and multipliers.
The whole idea of segregating the Costas loop has been explained earlier.
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The derived I and Q outputs are then passed through a bank of interpolator, filter and decimator which allow sampling rate conversion by non-integer factor.
The anti-aliasing FIR filter present in between the interpolator and the decimator is as explained earlier a Kaiser window, 64 tap filter designed to provide sufficient attenuation at stop band frequency of fs/2.
Figures 6, 7 show the amplitude response of the filter simulated in MATLAB for sampling frequencies of 112, 98 kHz respectively.
It uses same filter coefficients but gives the desired performance with changing sampling frequencies.
Figure 5.
Demodulator front end Figure 6.
Kaiser filter reponse for sampling frequency of 112 kHz Figure 7.
Kaiser filter reponse for sampling frequency of 98 kHz Refer to the figure 8, the I and Q outputs after the decimator are given to the PLL block which corrects for any residual phase and frequency offset between the incoming signal and the front end NCO in the IQ detector.
The NCO in this block is configured to work at Au0Ay frequency.
The in-phase arm of the PLL Realization of Programmable BPSK Demodulator-Bit Synchronizer using Multirate A (Anshuman Sharm.
A ISSN: 2088-8708 block gives the demodulated output.
Tha arm filters are 16 tap.
Kaiser window FIR filters which also get reconfigured with the change in sampling frequency.
The output is routed to an 8 bit Digital to Analog Converter (DAC) for monitoring purpose and also parallely to the bit synchronizer for clock and data Figure 9 shows the block diagram of the bit synchronizer.
The bit synchronizer does the clock recovery and also recovers the data.
Gardner algorithm is used for Timing Error Detection.
This algorithm is suitable for both tracking and acquisition modes of operation.
Also, the clock recovery does not depend on carrier phase.
In this algorithm, only two samples of the signal are required for each data symbol.
And also, one of the two samples is used for symbol strobing .
, the sample on which the symbol decision is mad.
The timing error detector operates upon samples and generates one error sample for each symbol.
This error sequence is smoothened by a loop filter and then used to adjust a timing error corrector, which in this case is an NCO.
The NCO is configured to run at a frequency which is double the discrete data rates as per the table With change in the sampling frequency, the NCO output frequency changes according to the sampling rate and the PLL locks for all the data rates between 1 kbps to 8 kbps as the loop filter is designed to achieve wide acquisition bandwidth .
For details on Gardner timing detector, refer to .
All the loop filters both in demodulator and bit synchronizer are first order lead-lag filters derived from their analog counter-part using bilinear transformation method.
Figure 8.
The PLL block Figure 9.
Bit synchronizer block diagram RESULTS AND ANALYSIS The demodulator-bit synchronizer was implemented on FPGA and the functionality was verified.
Figure 10 shows the output of the BPSK demodulator for 8 kbps data rate, routed through DAC.
The output is seen without an anti-imaging filter, so the sampling steps of 112 kHz are seen.
To verify the entire IJECE Vol.
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functionality a simulated modulated data with known Frame synchronization code was given as an input to the system and the bit sync data and clock output was given to an external frame synchronizer and continous frame sync lock was verified for all data rates from 1 kbps to 8 kbps.
Figure 10.
The BPSK demodulator- Output Eye diagram Programmabilty for Data Rates below 1 kbps Due to resource constraints on the FPGA, programmability for data rates from 8 kbps up to 100 bps could not be verified on hardware.
But individually selection for 100 bps data rate using the same architecture was verified on the FPGA.
The clock requirement for 100 bps data rate is shown in table 3.
we see that the ratio for interpolation to decimation is 1/160, additional decimation block of 160 was required for this data rate.
Also, a different anti-aliasing filter had to be used with stop band frequency at .
and pass band frequency at the data rate.
Table 3.
Clock requirement for 100 bps data rate
CONCLUSION
A detailed design and development of programmable BPSK demodulator- bit synchronizer using multirate processing has been demonstrated as a part of this work.
This work will be scaled for other carrier frequencies and other data rates in due course.
The whole focus of this work is programmability but the higher clock requirement of 32.
256 MHz can still be further optimized to a lower clock if the FIR filter in the demodulator front end is implemented with further parallelism and also the bit synchronizer is made to work with exactly two samples per bit.
ACKNOWLEDGEMENTS
We would like to express our sincere gratitude to Mr.
Govinda.
Deputy Director ICA.
Mr.
Sarma.
Group Director SCG.
Mr.
Raju Sagi.
Sci-Eng AuGAy and Mrs U.
Vasantha Kumari.
Head SRCD/SCG, for all the encouragement and technical guidance during the course of design and development.
We would like to specifically thank Mrs.
Vasuki E.
for precision fabrication expertise.
Realization of Programmable BPSK Demodulator-Bit Synchronizer using Multirate A (Anshuman Sharm.
A ISSN: 2088-8708
REFERENCES